Memory system and operation method thereof

ABSTRACT

A memory system may include: a nonvolatile memory; a volatile memory; and a controller suitable for repeatedly entering and exiting from an automatic exclusive mode for each predetermined size of write data transferred from the host in a start period of the automatic exclusive mode, and allocating the volatile memory exclusively for performing a merge operation on the nonvolatile memory during an entry period of the automatic exclusive mode, the controller may include a command queue for storing plural commands transferred from the host, may use a predetermined operation in the start period of the automatic exclusive mode to calculate a processing time of write commands among the commands stored in the command queue and an entry time of the entry period of the automatic exclusive mode, and may schedule a processing order of the commands stored in the command queue according to the calculation result.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2018-0031941 filed on Mar. 20, 2018, which isincorporated herein by reference in its entirety.

BACKGROUND 1. Field

Various embodiments of the present invention generally relate to amemory system. Particularly, the embodiments relate to a memory systemwhich supports a merge operation and command scheduling operation, andan operation method thereof.

2. Discussion of the Related Art

The computer environment paradigm has changed to ubiquitous computingthat allows computing systems to be used anytime and anywhere. As aresult, use of portable electronic devices such as mobile phones,digital cameras, and laptop computers has rapidly increased. Theseportable electronic devices generally use a memory system having one ormore memory devices for storing data. A memory system may be used as amain or an auxiliary storage device of a portable electronic device.

Memory systems provide excellent stability, durability, high informationaccess speed, and low power consumption because they have no movingparts (e.g., a mechanical arm with a read/write head) as compared with ahard disk device. Examples of memory systems having such advantagesinclude universal serial bus (USB) memory devices, memory cards havingvarious interfaces, and solid state drives (SSD).

SUMMARY

Various embodiments are directed to a memory system capable of improvingor maximizing the performance of a merge operation, and avoiding atimeout of a normal command requested from a host during the mergeoperation, and an operation method thereof.

In an embodiment, a memory system may include: a nonvolatile memorycomprising a plurality of memory blocks each having a plurality ofpages; a volatile memory suitable for temporarily storing data which aretransferred between a host and the nonvolatile memory; and a controllersuitable for repeatedly entering and exiting from an automatic exclusivemode for each predetermined size of write data transferred from the hostin a start period of the automatic exclusive mode, and allocating thevolatile memory exclusively for performing a merge operation on thenonvolatile memory during an entry period of the automatic exclusivemode, the controller may include a command queue for storing pluralcommands transferred from the host, may use a predetermined operation inthe start period of the automatic exclusive mode to calculate aprocessing time of write commands among the commands stored in thecommand queue and an entry time of the entry period of the automaticexclusive mode, and may schedule a processing order of the commandsstored in the command queue according to the calculation result.

The controller may select whether to start or end the automaticexclusive mode in response to a result obtained by checking the state ofthe nonvolatile memory, may enter the automatic exclusive mode when thewrite data corresponding to the write commands stored in the commandqueue are written by the preset size to the nonvolatile memory at anexit period of the automatic exclusive mode in the start period of theautomatic exclusive mode, and may exit from the automatic exclusive modeat a time point when a preset time has elapsed from the entry point ofthe automatic exclusive mode.

The memory system may further include an information storage suitablefor storing first information on the start and end states of theautomatic exclusive mode, second information on the entry and exitstates of the automatic exclusive mode and the preset size, and thirdinformation on the preset time.

The controller may include: a host controller comprising the commandqueue, and suitable for processing an operation between the host and thehost controller; a memory controller coupled to the host controller, andsuitable for processing an operation between the nonvolatile memory andthe memory controller, and the host controller may calculate theprocessing time and the entry time using the preset operation in thestart period of the automatic exclusive mode, and then may schedule theprocessing order of the commands stored in the command queue accordingto the calculation result.

The host controller may check the first to third information of theinformation storage, in the start period of the automatic exclusivemode, recognized through the check result, the host controller maycompare the preset size recognized through the check result, to anentire size of the write data corresponding to the write commands storedin the command queue, may calculate the number of entries going into andexiting from the automatic exclusive mode, which is required to processthe write commands stored in the command queue, as a processing numberaccording to the comparison result, and may calculate the processingtime by multiplying the processing number by a time required for writingthe preset size of write data to the nonvolatile memory.

The host controller may check the first to third information of theinformation storage, in the start period of the automatic exclusivemode, recognized through the check result, the host controller maycalculate the entry time by multiplying the preset time recognizedthrough the check result by the processing number.

The host controller may check the first to third information of theinformation storage, in the start period of the automatic exclusivemode, recognized through the check result, the host controller maycalculate a write time by adding the processing time and the entry time,may calculate an available processing time of other commands except thewrite commands among the commands stored in the command queue bysubtracting the write time from a timeout time of the write commandsstored in the command queue, may preferentially process the othercommands stored in the command queue until the available processingtime, and then may preferentially process the write commands stored inthe command queue.

The host controller may check the first to third information of theinformation storage, may inform the host of a switch of the memorysystem to a busy state in response to the entry into the automaticexclusive mode, recognized through the check result, and may inform thehost of a switch of the memory system to a ready state in response tothe exit from the automatic exclusive mode, recognized through the checkresult.

The memory controller may adjust the information on whether to start orend the automatic exclusive mode and the entry or exit points of theautomatic exclusive mode by adjusting the first to third information ofthe information storage in response to the result obtained by checkingthe state of the nonvolatile memory.

The memory controller may check the first to third information of theinformation storage, may write the write data to the nonvolatile memoryaccording to a request of the host controller at the exit period of theautomatic exclusive mode in the start period of the automatic exclusivemode, recognized through the check result, may enter the automaticexclusive mode by adjusting the second information of the informationstorage when the write data corresponding to the preset size recognizedthrough the check result are written to the nonvolatile memory, and mayexit from the automatic exclusive mode by adjusting the secondinformation of the information storage at a time point when that thepreset time recognized through the check result has elapsed from theentry point of the automatic exclusive mode.

In an embodiment, an operation method of a memory system which includesa nonvolatile memory including a plurality of blocks each having aplurality of pages, a volatile memory for temporarily storing datatransferred between a host and the nonvolatile memory, and a commandqueue for storing a plurality of commands transferred from the host, theoperation method may include: repeatedly entering and exiting from anautomatic exclusive mode for each predetermined size of write data whichare transferred from the host and written to the nonvolatile memory, ina start period of the automatic exclusive mode; exclusively using thevolatile memory to perform a merge operation on the nonvolatile memoryduring an entry period of the automatic exclusive mode; and calculatinga processing time of write commands among the commands stored in thecommand queue and an entry time of the entry period of the automaticexclusive mode, using a preset operation in the start period of theautomatic exclusive mode, and then scheduling a processing order of thecommands stored in the command queue according to the calculationresult.

The repeatedly entering the automatic exclusive mode may include:selecting whether to start or end the automatic exclusive mode inresponse to a result obtained by checking the state of the nonvolatilememory; entering the automatic exclusive mode when the write datacorresponding to the write commands stored in the command queue arewritten by the preset size to the nonvolatile memory at an exit periodof the automatic exclusive mode in the start period of the automaticexclusive mode, and exiting from the automatic exclusive mode at a timepoint when that a preset time has elapsed from the entry point of theautomatic exclusive mode.

The memory system may further include an information storage suitablefor storing first information on the start and end states of theautomatic exclusive mode, second information on the entry and exitstates of the automatic exclusive mode and the preset size, and thirdinformation on the preset time.

The memory system may further include a host controller suitable forprocessing an operation between the host and the host controller and amemory controller coupled to the host controller and suitable forprocessing an operation between the nonvolatile memory and the memorycontroller, and the operation processing step may include calculatingthe processing time and the entry time using the preset operationthrough the host controller in the start period of the automaticexclusive mode, and scheduling the processing order of the commandsstored in the command queue according to the calculation result.

The calculating the processing time may include a first check step inwhich the host controller checks the first to third information of theinformation storage, when it is checked through the first check stepthat the host controller is in the start period of the automaticexclusive mode, the calculating the processing time may further include:a first comparison step in which the host controller compares the presetsize recognized through the first check step to an entire size of thewrite data corresponding to the write commands stored in the commandqueue; a first calculation step in which the host controller calculatesthe number of entries going into and exiting from the automaticexclusive mode, which is required for processing the write commandsstored in the command queue, as a processing number according to theresult of the first comparison step; and a second calculation step inwhich the host controller calculates the processing time by multiplyingthe processing number by a time required for writing the preset size ofwrite data to the nonvolatile memory.

The calculating the processing time may further include a thirdcalculation step in which the host controller calculates the entry timeby multiplying the preset time recognized through the first check stepby the processing number, when it is checked through the first checkstep that the host controller is in the start period of the automaticexclusive mode.

The calculating the processing time may include: a fourth calculationstep in which the host controller calculates a write time by adding theprocessing time and the entry time, when it is checked at the firstcheck step that the host controller is in the start period of theautomatic exclusive mode; a fifth calculation step in which the hostcontroller calculates an available processing time of the other commandsexcept the write commands among the commands stored in the command queueby subtracting the write time from a timeout time of the write commandsstored in the command queue; and a processing step in which the hostcontroller preferentially processes the other commands stored in thecommand queue until the available processing time, and thenpreferentially processes the write commands stored in the command queue.

The repeatedly entering the automatic exclusive mode may include: asecond check step in which the host controller checks the first to thirdinformation of the information storage; a first informing step in whichthe host controller informs the host of a switch of the memory system toa busy state in response to an entry of the automatic exclusive mode,recognized through the second check state; and a second informing stepin which the host controller informs the host of a switch of the memorysystem to a ready state in response to an exit of the automaticexclusive mode, recognized through the second check state.

The repeatedly entering the automatic exclusive mode may include: athird check step in which the memory controller checks the state of thenonvolatile memory; and an adjusting step in which the memory controlleradjusts the information on whether to start or end the automaticexclusive mode and the entry or exit points of the automatic exclusivemode by adjusting the first to third information of the informationstorage in response to the result of the third check step.

The repeatedly entering the automatic exclusive mode may further includea fourth check step in which the memory controller checks the first tothird information of the information storage, the entry step mayinclude: writing, by the memory controller, the write data to thenonvolatile memory according to a write request transferred to thememory controller from the host controller at an exit period of theautomatic exclusive mode in the start period of the automatic exclusivemode, recognized through the result of the fourth check step; andentering, by the memory controller, the automatic exclusive mode byadjusting the second information of the information storage when thememory controller writes the write data corresponding to the preset sizerecognized through the result of the fourth check step to thenonvolatile memory, and in the exit step, the memory controller may exitfrom the automatic exclusive mode by adjusting the second information ofthe information storage at a time point when the preset time recognizedthrough the result of the fourth check step has elapsed from the entrypoint of the automatic exclusive mode.

In an embodiment, a memory system may include: a nonvolatile memorycomprising a plurality of memory blocks, each having a plurality ofpages; a volatile memory suitable for temporarily storing data which aretransferred between a host and the nonvolatile memory; and a controllercomprising a command queue for storing a plurality of commands enteredfrom the host, a volatile memory used for performing a merge operationduring an entry period of the automatic exclusive mode, and at least onebuffer used for re-scheduling a processing order of the plurality ofcommands stored in the command queue, a controller may be suitable forstoring a write data entered from a host into the volatile memory,dividing the write data by a predetermined size, carrying out andstopping an automatic exclusive mode for each predetermined size ofwrite data.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features and advantages of the present invention willbecome apparent to those skilled in the art to which the presentinvention pertains from the following detailed description in referenceto the accompanying drawings, wherein:

FIG. 1 is a block diagram illustrating a data processing systemincluding a memory system in accordance with an embodiment of thepresent invention;

FIG. 2 is a schematic diagram illustrating a configuration of a memorydevice employed in the memory system shown in FIG. 1;

FIG. 3 is a circuit diagram illustrating a configuration of a memorycell array of a memory block in the memory device shown in FIG. 2;

FIG. 4 is a schematic diagram illustrating a three-dimensional (3D)structure of the memory device shown in FIG. 2;

FIGS. 5 to 7 are diagrams describing a memory system in accordance withan embodiment; and

FIGS. 8 to 16 are diagrams schematically illustrating applicationexamples of the data processing system shown in FIG. 1 in accordancewith various embodiments of the present invention.

DETAILED DESCRIPTION

Various embodiments of the present invention are described below in moredetail with reference to the accompanying drawings. We note, however,that the present invention may be embodied in different otherembodiments, forms and variations thereof and should not be construed asbeing limited to the embodiments set forth herein. Rather, the describedembodiments are provided so that this disclosure will be thorough andcomplete, and will fully convey the present invention to those skilledin the art to which this invention pertains. Throughout the disclosure,like reference numerals refer to like parts throughout the variousfigures and embodiments of the present invention. It is noted thatreference to “an embodiment” does not necessarily mean only oneembodiment, and different references to “an embodiment” are notnecessarily to the same embodiment(s).

It will be understood that, although the terms “first”, “second”,“third”, and so on may be used herein to describe various elements,these elements are not limited by these terms. These terms are used todistinguish one element from another element. Thus, a first elementdescribed below could also be termed as a second or third elementwithout departing from the spirit and scope of the present invention.

The drawings are not necessarily to scale and, in some instances,proportions may have been exaggerated in order to clearly illustratefeatures of the embodiments.

It will be further understood that when an element is referred to asbeing “connected to”, or “coupled to” another element, it may bedirectly on, connected to, or coupled to the other element, or one ormore intervening elements may be present. In addition, it will also beunderstood that when an element is referred to as being “between” twoelements, it may be the only element between the two elements, or one ormore intervening elements may also be present.

The terminology used herein is for describing particular embodimentsonly and is not intended to be limiting of the present invention. Asused herein, singular forms are intended to include the plural forms andvice versa, unless the context clearly indicates otherwise. It will befurther understood that the terms “comprises,” “comprising,” “includes,”and “including” when used in this specification, specify the presence ofthe stated elements and do not preclude the presence or addition of oneor more other elements. As used herein, the term “and/or” includes anyand all combinations of one or more of the associated listed items.

Unless otherwise defined, all terms including technical and scientificterms used herein have the same meaning as commonly understood by one ofordinary skill in the art to which the present invention belongs in viewof the disclosure. It will be further understood that terms, such asthose defined in commonly used dictionaries, should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthe disclosure and the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

In the following description, numerous specific details are set forth inorder to provide a thorough understanding of the invention. Theinvention may be practiced without some or all of these specificdetails. In other instances, well-known process structures and/orprocesses have not been described in detail in order not tounnecessarily obscure the invention.

It is also noted, that in some instances, as would be apparent to thoseskilled in the relevant art, a feature or element described inconnection with one embodiment may be used singly or in combination withother features or elements of another embodiment, unless otherwisespecifically indicated.

Hereinafter, the various embodiments of the present invention will bedescribed in detail with reference to the attached drawings.

FIG. 1 is a block diagram illustrating a data processing system 100including a memory system 110 in accordance with an embodiment of theinvention.

Referring to FIG. 1, the data processing system 100 may include a host102 and the memory system 110.

The host 102 may include portable electronic devices such as a mobilephone, MP3 player and laptop computer or non-portable electronic devicessuch as a desktop computer, a game machine, a TV and a projector.

The memory system 110 may operate to store data for the host 102 inresponse to a request of the host 102. Non-limiting examples of thememory system 110 may include a solid state drive (SSD), a multi-mediacard (MMC), a secure digital (SD) card, a universal storage bus (USB)device, a universal flash storage (UFS) device, compact flash (CF) card,a smart media card (SMC), a personal computer memory card internationalassociation (PCMCIA) card and memory stick. The MMC may include anembedded MMC (eMMC), reduced size MMC (RS-MMC) and micro-MMC. The SDcard may include a mini-SD card and micro-SD card.

The memory system 110 may be embodied by various types of storagedevices. Non-limiting examples of storage devices included in the memorysystem 110 may include volatile memory devices such as a DRAM dynamicrandom access memory (DRAM) and a static RAM (SRAM) and nonvolatilememory devices such as a read only memory (ROM), a mask ROM (MROM), aprogrammable ROM (PROM), an erasable programmable ROM (EPROM), anelectrically erasable programmable ROM (EEPROM), a ferroelectric RAM(FRAM), a phase-change RAM (PRAM), a magneto-resistive RAM (MRAM), aresistive RAM (RRAM) and a flash memory. The flash memory may have a3-dimensional (3D) stack structure.

The memory system 110 may include a memory device 150 and a controller130. The memory device 150 may store data for the host 120. Thecontroller 130 may control data storage into the memory device 150.

The controller 130 and the memory device 150 may be integrated into asingle semiconductor device, which may be included in the various typesof memory systems as exemplified above.

Non-limiting application examples of the memory system 110 may include acomputer, an Ultra Mobile PC (UMPC), a workstation, a net-book, aPersonal Digital Assistant (PDA), a portable computer, a web tablet, atablet computer, a wireless phone, a mobile phone, a smart phone, ane-book, a Portable Multimedia Player (PMP), a portable game machine, anavigation system, a black box, a digital camera, a Digital MultimediaBroadcasting (DMB) player, a 3-dimensional television, a smarttelevision, a digital audio recorder, a digital audio player, a digitalpicture recorder, a digital picture player, a digital video recorder, adigital video player, a storage device constituting a data center, adevice capable of transmitting/receiving information in a wirelessenvironment, one of various electronic devices constituting a homenetwork, one of various electronic devices constituting a computernetwork, one of various electronic devices constituting a telematicsnetwork, a Radio Frequency Identification (RFID) device, or one ofvarious components constituting a computing system.

The memory device 150 may be a nonvolatile memory device and may retaindata stored therein even though power is not supplied. The memory device150 may store data provided from the host 102 through a write operation.The memory device 150 may provide data stored therein to the host 102through a read operation. The memory device 150 may include a pluralityof memory dies (not shown), each memory die including a plurality ofplanes (not shown), each plane including a plurality of memory blocks152 to 156. Each of the memory blocks 152 to 156 may include a pluralityof pages. Each of the pages may include a plurality of memory cellscoupled to a word line.

The controller 130 may control the memory device 150 in response to arequest from the host 102. By way of example and not limitation, thecontroller 130 may provide data read from the memory device 150 to thehost 102, and store data provided from the host 102 into the memorydevice 150. For this operation, the controller 130 may control read,write, program and erase operations of the memory device 150.

The controller 130 may include a host interface (I/F) 132, a processor134, an error correction code (ECC) component 138, a Power ManagementUnit (PMU) 140, a memory interface 142 such as a NAND flash controller(NFC), and a memory 144. Each of components may be electrically coupled,or engaged with, each other via an internal bus.

The host interface 132 may be configured to process a command and dataof the host 102, and may communicate with the host 102 under one or moreof various interface protocols such as universal serial bus (USB),multi-media card (MMC), peripheral component interconnect-express (PCI-eor PCIe), small computer system interface (SCSI), serial-attached SCSI(SAS), serial advanced technology attachment (SATA), parallel advancedtechnology attachment (DATA), enhanced small disk interface (ESDI) andintegrated drive electronics (IDE).

The ECC component 138 may detect and correct an error contained in thedata read from the memory device 150. In other words, the ECC component138 may perform an error correction decoding process to the data readfrom the memory device 150 through an ECC code used during an ECCencoding process. According to a result of the error correction decodingprocess, the ECC component 138 may output a signal, for example, anerror correction success or fail signal. When the number of error bitsis more than a threshold value of correctable error bits, the ECCcomponent 138 may not correct the error bits to output the errorcorrection fail signal.

The ECC component 138 may perform error correction through a codedmodulation such as Low Density Parity Check (LDDC) code,Bose-Chaudhri-Hocquenghem (BCH) code, turbo code, Reed-Solomon code,convolution code, Recursive Systematic Code (RSC), Trellis-CodedModulation (TCM) and Block coded modulation (BCM). However, the ECCcomponent 138 is not limited thereto. The ECC component 138 may includeall circuits, modules, systems or devices for error correction.

The PMU 140 may manage an electrical power used and provided in thecontroller 130.

The memory interface 142 may serve as a memory/storage interface forinterfacing the controller 130 and the memory device 150 such that thecontroller 130 controls the memory device 150 in response to a requestfrom the host 102. When the memory device 150 is a flash memory orspecifically a NAND flash memory, the memory interface 142 may generatea control signal for the memory device 150 to process data entered intothe memory device 150 by the processor 134. The memory interface 142 maywork as an interface (e.g., a NAND flash interface) for processing acommand and data between the controller 130 and the memory device 150.Specifically, the memory interface 142 may support data transfer betweenthe controller 130 and the memory device 150.

The memory 144 may serve as a working memory of the memory system 110and the controller 130. The memory 144 may store data supportingoperation of the memory system 110 and the controller 130. Thecontroller 130 may control the memory device 150 so that read, write,program and erase operations are performed in response to a request fromthe host 102. The controller 130 may provide data read from the memorydevice 150 to the host 102, and may store data provided from the host102 into the memory device 150. The memory 144 may store data requiredfor the controller 130 and the memory device 150 to perform theseoperations.

The memory 144 may be embodied by a volatile memory. By way of exampleand not limitation, the memory 144 may be embodied by static randomaccess memory (SRAM) or dynamic random access memory (DRAM). The memory144 may be disposed within or out of the controller 130. FIG. 1describes an example of the memory 144 disposed within the controller130. In another embodiment, the memory 144 may be embodied by anexternal volatile memory having a memory interface 142 transferring databetween the memory 144 and the controller 130.

The processor 134 may control the overall operations of the memorysystem 110. The processor 134 may use a firmware to control the overalloperations of the memory system 110. The firmware may be referred to asflash translation layer (FTL).

The processor 134 of the controller 130 may include a management unit(not illustrated) for performing a bad management operation of thememory device 150. The management unit may perform a bad blockmanagement operation of checking a bad block among the plurality ofmemory blocks 152 to 156 included in the memory device 150. The badblock may include a block where a program fail occurs during a programoperation, due to the characteristics of a NAND flash memory. Themanagement unit may write the program-failed data of the bad block to anew memory block. In the memory device 150 having a 3D stack structure,the bad block management operation may reduce the use efficiency of thememory device 150 and the reliability of the memory system 110. Thus,the bad block management operation needs to be performed with morereliability.

FIG. 2 is a schematic diagram illustrating the memory device 150 shownin FIG. 1.

Referring to FIG. 2, the memory device 150 may include a plurality ofmemory blocks BLOCK0 to BLOCKN−1, and each of the blocks BLOCK0 toBLOCKN−1 may include a plurality of pages, for example, 2^(M) pages, thenumber of which may vary according to circuit design. Memory cellsincluded in the respective memory blocks 0 to N−1 may be one or more ofa single level cell (SLC) storing 1-bit data, or a multi-level cell(MLC) storing 2- or more bit data. In an embodiment, the memory device150 may include a plurality of triple level cells (TLC) each storing3-bit data. In another embodiment, the memory device may include aplurality of quadruple level cells (QLC) each storing 4-bit level cell.

FIG. 3 is a circuit diagram illustrating a configuration of a memorycell array of a memory block in the memory device 150.

Referring to FIG. 3, a memory block 330 which may correspond to any ofthe plurality of memory blocks 152 to 156 included in the memory device150 of the memory system 110 may include a plurality of cell strings 340coupled to a plurality of corresponding bit lines BL0 to BLm−1. The cellstring 340 of each column may include one or more drain selecttransistors DST and one or more source select transistors SST. Betweenthe drain and source select transistors DST, SST, a plurality of memorycells MC0 to MCn−1 may be coupled in series. In an embodiment, each ofthe memory cell transistors MC0 to MCn−1 may be embodied by an MLCcapable of storing data information of a plurality of bits. Each of thecell strings 340 may be electrically coupled to a corresponding bit lineamong the plurality of bit lines BL0 to BLm−1. For example, asillustrated in FIG. 3, the first cell string is coupled to the first bitline BL0, and the last cell string is coupled to the last bit lineBLm−1. For reference, in FIG. 3, ‘DSL’ denotes a drain select line,‘SSL’ denotes a source select line, and ‘CSL’ denotes a common sourceline. A plurality of world lines WL0 to WLn−1 may be coupled in seriesbetween the select source line SSL and the drain source line DSL.

Although FIG. 3 illustrates NAND flash memory cells, the invention isnot limited in this way. It is noted that the memory cells may be NORflash memory cells, or hybrid flash memory cells including two or morekinds of memory cells combined therein. Also, it is noted that thememory device 150 may be a flash memory device including a conductivefloating gate as a charge storage layer or a charge trap flash (CTF)memory device including an insulation layer as a charge storage layer.

The memory device 150 may further include a voltage supply 310 whichprovides word line voltages including a program voltage, a read voltageand a pass voltage to supply to the word lines according to an operationmode. The voltage generation operation of the voltage supply 310 may becontrolled by a control circuit (not illustrated). Under the control ofthe control circuit, the voltage supply 310 may select one of the memoryblocks (or sectors) of the memory cell array, select one of the wordlines of the selected memory block, and provide the word line voltagesto the selected word line and the unselected word lines as may beneeded.

The memory device 150 may include a read and write circuit (read/write)320 which is controlled by the control circuit. During averification/normal read operation, the read/write circuit 320 mayoperate as a sense amplifier for reading data from the memory cellarray. During a program operation, the read/write circuit 320 mayoperate as a write driver for driving bit lines according to data to bestored in the memory cell array. During a program operation, theread/write circuit 320 may receive from a buffer (not illustrated) datato be stored into the memory cell array, and may supply a current or avoltage onto bit lines according to the received data. The read/writecircuit 320 may include a plurality of page buffers 322 to 326respectively corresponding to columns (or bit lines) or column pairs (orbit line pairs). Each of the page buffers 322 to 326 may include aplurality of latches (not illustrated).

FIG. 4 is a schematic diagram illustrating a three-dimensional (3D)structure of the memory device 150 shown in FIGS. 1 to 3.

The memory device 150 may be embodied by a two-dimensional (2D) or a 3Dmemory device. Specifically, as illustrated in FIG. 4, the memory device150 may be embodied by a nonvolatile memory device having a 3D stackstructure. When the memory device 150 has a 3D structure, the memorydevice 150 may include a plurality of memory blocks BLK0 to BLKN−1 eachhaving a 3D structure (or vertical structure). The plurality of memoryblocks BLK0 to BLKN−1 may correspond to the memory blocks BLOCK0 toBLOCKN−1 shown in FIG. 2.

Hereinbelow, detailed descriptions will be made with reference to FIGS.5 to 8, for data processing with respect to the memory device 150 in amemory system in accordance with an embodiment, particularly, a dataprocessing operation when performing a command operation correspondingto a command received from the host 102 and a data management operation.

FIGS. 5 to 7 are diagrams describing an operation of a memory system 110in accordance with an embodiment.

FIGS. 5 to 7 illustrate a configuration of a data processing system 100including a host 102 and a memory system 110 with reference to theconfiguration of the data processing system 100 illustrated in FIG. 1.

As described with reference to FIG. 1, the memory system 110 may includea controller 130 and a nonvolatile memory 150.

The controller 130 may include a processor 134, a volatile memory 144and an information storage 530. The processor 134 may include a hostcontroller 510 and a memory controller 520. The host controller 510 mayinclude a command queue 512.

The nonvolatile memory 150 may include a plurality of memory blocksBLOCK<1:6>. The plurality of memory blocks <1:6> may correspond to thememory blocks 152 to 156 described in FIG. 1. At this time, each of thememory blocks BLOCK<1:6> may include a plurality of pages as describedwith reference to FIG. 2.

Although FIGS. 5 to 7 illustrate that the memory system 110 includesonly one nonvolatile memory 150, the present invention is not limitedthereto. That is, this configuration is only an example for convenienceof description, and a larger number of nonvolatile memories may beincluded in the memory system 110. Furthermore, although FIGS. 5 to 7illustrate that the nonvolatile memory 150 includes six memory blocksBLOCK<1:6>, the present invention is not limited thereto. That is, thisconfiguration is only an example for convenience of description, and thenumber of memory blocks included in the nonvolatile memory 150 may varydepending on design.

While FIG. 1 illustrates that the host interface 132, the ECC component138, the power management unit 140, and the memory interface 142 areincluded in the controller 130, FIGS. 5 to 7 illustrate only some of thecomponents included in the controller 130. However, those components areonly omitted for convenience of description, and may be actuallyincluded in the controller 130.

The volatile memory 144 may temporarily store data transferred betweenthe host 102 and the nonvolatile memory 150. At this time, the volatilememory 144 may correspond to the memory 144 described with reference toFIG. 1. Although FIG. 5 illustrates that the volatile memory 144 isincluded in the controller 130, the present invention is not limitedthereto. That is, the volatile memory 144 may be installed outside thecontroller 130 in the memory system 110.

The controller 130 may select whether to start/end an automaticexclusive mode in response to a result obtained by checking the state ofthe nonvolatile memory 150, at operation 1301. Herein, the automaticexclusive mode may support that the controller 130 may temporarilysuspend or halt carrying out a request entered from the host 102 for aninternal operation in the memory system 110.

When the automatic exclusive mode is starts as a result of operation1301, that is, during a start period of the automatic exclusive mode,the controller 130 may repeatedly enter/exit from the automaticexclusive mode for every preset size of write data transferred from thehost 102, at operation 1302. The controller 130 may divide the writedata by a preset or predetermined size.

Specifically, at an exit period of the automatic exclusive mode in thestart period of the automatic exclusive mode through operation 1301, thecontroller 130 in operation 1302 may re-enter the automatic exclusivemode, at operation 1306, when write data transferred from the host 102are written by the preset size to the nonvolatile memory 150 from anescaped state where the controller 130 exits from the automaticexclusive mode at operation 1307 which will be described later.

The controller 130 in operation 1302 may exit from the automaticexclusive mode at a time point when a preset time elapses from an entrypoint of the automatic exclusive mode in the start period of theautomatic exclusive mode through operation 1301, that is, the entrypoint of the automatic exclusive mode through operation 1306, atoperation 1307.

The controller 130 may further include a command queue 512 for storing aplurality of commands entered from the host 102. In operation 1303, thecontroller 130 may store the plurality of commands entered from the host102 in the command queue 512.

The controller 130 in operation 1306 including operation 1303 may startthe automatic exclusive mode, when a write data corresponding to a writecommand among the commands which are transferred from the host 102 andstored in the command queue 512 is written by the preset size to thenonvolatile memory 150 during the exit period of the automatic exclusivemode in the start period of the automatic exclusive mode throughoperation 1301, or after the controller 130 exits from the automaticexclusive mode through operation 1307. That is, the automatic exclusivemode may be re-started, or re-entered, after a predetermined-size writedata is programmed into the nonvolatile memory 150 for the escapedstate, i.e., a period of ceasing or halting the automatic exclusivemode.

The controller 130 may calculate and/or estimate a processing time ofthe write command among the commands stored in the command queue 512 aswell as an entry time of the automatic exclusive mode, using a presetoperation in the start period of the automatic exclusive mode throughoperation 1301, at operation 1304.

The controller 130 may schedule a processing order of the commandsstored in the command queue 512 according to the calculation result ofoperation 1304 in the start period of the automatic exclusive modethrough operation 1301, at operation 1305. In order to re-schedule aprocessing order of the commands stored in the command queue 512, in anembodiment, the controller 130 may include at least one buffer (notshown).

At the entry period of the automatic exclusive mode through operation1306 of operation 1302 in the start period of the automatic exclusivemode through operation 1301, the controller 130 may exclusively use thevolatile memory 144 to perform a merge operation on the nonvolatilememory 150 at operation 1308.

Specifically, the controller 130 may flush data stored in the volatilememory 144 to the nonvolatile memory 150 in response to the entry intothe automatic exclusive mode through operation 1306 of operation 1302 inthe start period of the automatic exclusive mode through operation 1301.

In this case, the controller 130 may exclusively use the entire regionof the volatile memory 144 to perform the merge operation during theentry period of the automatic exclusive mode.

At this time, the operation of flushing the data stored in the volatilememory 144 to the nonvolatile memory 150 may indicate that all datastored in the volatile memory 144 are copied and stored into a presetregion of the nonvolatile memory 150. After the flush operation, alldata in the volatile memory 144 are no longer necessary to be retainedso that the controller 130 may discard all data stored in the volatilememory 144. Then, the controller 130 may exclusively use the entireregion of the volatile memory 144, which is allocated for storing data,to perform a merge operation.

Furthermore, the controller 130 may discard data updated into thenonvolatile memory 150 among the data stored in the volatile memory 144,in response to the entry into the automatic exclusive mode throughoperation 1306 of operation 1302 in the start period of the automaticexclusive mode through operation 1301.

In this case, the controller 130 may exclusively use a region coveringmore than a designated region for a general merge operation in thevolatile memory 144, to perform the merge operation during the entryperiod of the automatic exclusive mode.

As described above with reference to FIG. 1, the volatile memory 144 canbe used for various uses, for example, a write buffer/cache, a readbuffer/cache, and a map buffer/cache. Therefore, the internal storagespace of the volatile memory 144 may be divided into various regionsdepending on the uses. Thus, a part of the internal storage region ofthe volatile memory 144 may be previously designated for a mergeoperation.

At this time, the controller 130 in accordance with the presentembodiment may discard data updated into the nonvolatile memory 150among data stored in a region which is not designated for a mergeoperation in the storage space of the volatile memory 144, in responseto the entry into the automatic exclusive mode through operation 1306 ofoperation 1302. Therefore, the controller 130 in accordance with thepresent embodiment can exclusively use a wider region than the regiondesignated for a general merge operation in the volatile memory 144, toperform a merge operation during the entry period of the automaticexclusive mode.

The data updated into the nonvolatile memory 150 among the data storedin the volatile memory 144 may indicate data which have been alreadystored into the nonvolatile memory 150 through an operation such as acheckpoint, among the data stored in the nonvolatile memory 144. Forthis reason, the controller 130 can discard the data updated into thenonvolatile memory 150 among the data stored in the volatile memory 144in the entry period of the automatic exclusive mode, and then use thecorresponding region for a merge operation.

The controller 130 may switch the state of the memory system 110 to abusy state and inform the host 102 of the switched state, in response tothe entry into the automatic exclusive mode through operation 1306 ofoperation 1302 in the start period of the automatic exclusive modethrough operation 1301.

Since the host 102 recognizes through the operation of the controller130 that the memory system 110 is busy, the controller 130 may notreceive an arbitrary request such as a read request or a write requestentered from the host 102 for the entry or start period of the automaticexclusive mode through operation 1306 of operation 1302.

The controller 130 may switch the state of the memory system 110 to aready state and inform the host 102 of the switched state (i.e., theready state), in response to the exit from the automatic exclusive modethrough operation 1307 of operation 1302 in the start period of theautomatic exclusive mode through operation 1301.

Since the host 102 recognizes through the operation of the controller130 that the memory system 110 is ready, the controller 130 may receivean arbitrary request such as a read request or a write request enteredfrom the host 102 after exiting from the automatic exclusive modethrough operation 1307 of operation 1302.

The merge operation may include an operation of merging valid dataincluded in two or more victim memory blocks among the memory blocksBLOCK<1:6> included in the nonvolatile memory 150, and another operationof moving the merged data to a target memory block.

By way of example and not limitation, the merge operation may include agarbage collection operation, a read reclaim operation, a wear levelingoperation or a map update operation. Alternatively, the merge operationmay work as a partial process for the garbage collision operation, theread reclaim operation, the wear leveling operation or the map updateoperation.

As described above, the controller 130 may determine whether tostart/end the automatic exclusive mode, according to the result obtainedby checking the state of the nonvolatile memory 150, at operation 1301.

At this time, the operation of checking the state of the nonvolatilememory 150 may include an operation of checking the ratio of free memoryblocks among the memory blocks BLOCK<1:6> included in the nonvolatilememory 150.

That is, to check the state of the nonvolatile memory 150, thecontroller 130 may check the ratio of free memory blocks among thememory blocks BLOCK<1:6> included in the nonvolatile memory 150. Thecontroller 130 may determine whether to start/end the automaticexclusive mode according to the check result.

When the check result indicates that the ratio of free memory blocks isequal to or less than a preset ratio, the controller 130 maycontinuously retain the automatic exclusive mode in the case where theautomatic exclusive mode was already started. The controller 130 maystart the automatic exclusive mode in the case where the automaticexclusive mode was ended. Thus, the entry/exit of the automaticexclusive mode through operation 1302 may be repeated.

On the other hand, when the check result indicates that the ratio offree memory blocks exceeds the preset ratio, the controller 130 may endthe automatic exclusive mode in the case where the automatic exclusivemode was already started. The controller 130 may also retain the endstate of the automatic exclusive mode in the case where the automaticexclusive mode was ended. Thus, the entry/exit of the automaticexclusive mode through operation 1302 may not be repeated.

In the embodiment, the operation of checking the ratio of free memoryblocks among the memory blocks BLOCK<1:6> included in the nonvolatilememory 150 may be exemplified as the operation of checking the state ofthe nonvolatile memory 150. However, this is only an example, and thestate of the nonvolatile memory 150 can be checked through anothermethod.

The information storage 530 may store first information corresponding tooperation 1301 of the controller 130 as well as second and thirdinformation corresponding to operation 1302 of the controller 130.

The first information may contain information indicating whether theautomatic exclusive mode was started or ended through operation 1301 ofthe controller 130.

The second information may contain information on ‘preset size’ used asan entry condition of the automatic exclusive mode in operation 1306 ofoperation 1302, and the information indicating whether the controller130 entered or exited from the automatic exclusive mode throughoperation 1302.

The third information may contain information on ‘preset time’ of theautomatic exclusive mode, which indicates at which point the controller130 will exit from the automatic exclusive mode through operation 1307of operation 1302, after entering the automatic exclusive mode throughoperation 1306 of operation 1302, regarding the automatic exclusive modestarted through operation 1301 of the controller 130.

At this time, the controller 130 may control operations 1301 and 1302 byreferring to the first to third information stored in the informationstorage 530.

That is, the controller 130 may check the first to third informationstored in the information storage 530, enter the automatic exclusivemode when the preset size of write data are transferred from the host102 and written to the nonvolatile memory 150 through operation 1306 ofoperation 1302 in the start period of the automatic exclusive modethrough operation 1301, which can be recognized through the checkresult, and exit from the automatic exclusive mode at a point of timethat a preset time has elapsed from the entry point of the automaticexclusive mode through operation 1307 of operation 1302.

Specifically, the controller 130 may check whether the automaticexclusive mode was already started, by referring to the firstinformation stored in the information storage 530.

When the check result indicates that the automatic exclusive mode is notstarted or the automatic exclusive mode was ended, the controller 130may perform operation 1301 to select whether to start the automaticexclusive mode. On the other hand, the controller 130 may performoperation 1301 to continuously retain the end state of the automaticexclusive mode.

When the check result indicates that the automatic exclusive mode wasstarted, the controller 130 may perform operation 1301 to determinewhether to end the automatic exclusive mode. On the other hand, thecontroller 130 may perform operation 1301 to continuously retain theautomatic exclusive mode.

When the result obtained by checking the first information stored in theinformation storage 530 indicates that the automatic exclusive mode wasstarted, the controller 130 may check the entry/exit states andentry/exit points (i.e., time points) of the automatic exclusive mode byreferring to the second and third information. For example, thecontroller 130 may check the second information of the informationstorage 530 in the start period of the automatic exclusive mode. Whenthe check result indicates that the controller 130 exited from theautomatic exclusive mode, the controller 130 may check the size of writedata corresponding to write commands stored in the command queue 512,and check a time point of when the automatic exclusive mode was entered.Similarly, the controller 130 may check the second information stored inthe information storage 530 in the start period of the automaticexclusive mode. When the check result indicates that the controller 130entered the automatic exclusive mode, the controller 130 may check thethird information stored in the information storage 530 and check a timepoint of when the automatic exclusive mode was exited.

The controller 130 may adjust the values of the first to thirdinformation stored in the information storage 530, in response to theresult obtained by checking the state of the nonvolatile memory 150.

Specifically, the controller 130 may adjust the value of the firstinformation stored in the information storage 530 according to theresult obtained by checking the state of the nonvolatile memory 150 asdescribed above at operation 1301. The controller 130 may determinewhether to start/end the automatic exclusive mode. By way of example andnot limitation, when the controller 130 needs to start the automaticexclusive mode according to the result obtained by checking the ratio offree memory blocks among the memory blocks BLOCK<1:6> included in thenonvolatile memory 150, the controller 130 may set the first informationstored in the information storage 530 to the start state. Similarly,when the controller 130 needs to end the automatic exclusive modeaccording to the result obtained by checking the ratio of free memoryblocks among the memory blocks BLOCK<1:6> included in the nonvolatilememory 150, the controller 130 may set the first information stored inthe information storage 530 to the end state.

According to the result obtained by checking the state of thenonvolatile memory 150 in the start period of the automatic exclusivemode, the controller 130 may adjust the value of the second or thirdinformation stored in the information storage 530.

Specifically, when entering the automatic exclusive mode to perform amerge operation through operation 1306 of operation 1302 in the startperiod of the automatic exclusive mode, the controller 130 may adjustthe value of the second or third information stored in the informationstorage 530 according to a result obtained by checking the total numberof valid pages included in victim memory blocks among the memory blocksBLOCK<1:6> included in the nonvolatile memory 150.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is equal to or more than a presetnumber, the controller 130 may decrease the preset size contained in thesecond information stored in the information storage 530, such that theentry into the automatic exclusive mode through operation 1306 is morefrequently repeated.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is less than the preset number,the controller 130 may increase the preset size contained in the secondinformation stored in the information storage 530, such that the entryinto the automatic exclusive mode through operation 1306 is lessfrequently repeated.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is equal to or more than thepreset number, the controller 130 may increase the preset lengthcontained in the third information stored in the information storage530, such that the time interval from the entry point of the automaticexclusive mode through operation 1306 to the exit point of the automaticexclusive mode through operation 1307 is increased.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is less than the preset number,the controller 130 may decrease the preset length contained in the thirdinformation stored in the information storage 530, such that the timeinterval from the entry point of the automatic exclusive mode throughoperation 1306 to the exit point of the automatic exclusive mode throughoperation 1307 is decreased.

For reference, the controller 130 may adjust only the second or thirdinformation or both of the second and third information stored in theinformation storage 530 through one adjusting operation. The adjustingoperation of the controller 130 to adjust the second or thirdinformation stored in the information storage 530 may vary depending ondesign.

In the above-described embodiment, ‘preset ratio’ and ‘preset number’have been exemplified as reference values for adjusting the first tothird information stored in the information storage 530. However, thevalues are only examples, and more types of reference values can beused. For example, ‘first to N ratios’ and ‘first to M numbers’ can beused where N and M are natural numbers larger than 2.

As described above at operation 1304, the controller 130 may calculatethe processing time of the write commands among the commands stored inthe command queue 512 and the entry time of the entry period of theautomatic exclusive mode, using the preset operation in the start periodof the automatic exclusive mode through operation 1301.

Furthermore, as described above at operation 1305, the controller 130may schedule the processing order of the commands stored in the commandqueue 512 according to the calculation result of operation 1304.

Specifically, the controller 130 may check the first to thirdinformation stored in the information storage 530. At this time, whenthe result obtained by checking the first information stored in theinformation storage 530 indicates that the automatic exclusive mode wasstarted, the controller 130 may additionally check the second and thirdinformation stored in the information storage 530 to perform the presetoperation. On the other hand, when the result indicates that theautomatic exclusive mode was ended, the controller 130 may not check thesecond and third information stored in the information storage 530 andthe preset operation may not be performed.

Therefore, when the result obtained by checking the first informationstored in the information storage 530 indicates that the automaticexclusive mode was started, the controller 130 may compare the presetsize recognized through the result obtained by checking the secondinformation stored in the information storage 530 to the entire size ofthe write data corresponding to the write commands among the commandsstored in the command queue 512, and calculate the number of entriesinto/exits from the automatic exclusive mode, which is required forprocessing the write commands stored in the command queue 512, as aprocessing number according to the comparison result.

The controller 130 may calculate the processing time of the writecommands stored in the command queue 512 by multiplying the number ofentries into/exits from the automatic exclusive mode, which is requiredfor processing the write commands stored in the command queue 512, bythe time required for writing the preset size of write data to thenonvolatile memory 150.

The controller 130 may calculate the entry time of the entry period ofthe automatic exclusive mode which is repeated while the write commandsstored in the command queue 512 are processed, by multiplying the numberof entries into/exits from the automatic exclusive mode, which isrequired for processing the write commands stored in the command queue512, by the preset time which can be recognized as the result obtainedby checking the third information stored in the information storage 530.

The controller 130 may calculate a write time required for processingthe write commands stored in the command queue 512 by adding theprocessing time of the write commands stored in the command queue 512and the entry time of the entry period of the automatic exclusive periodwhich is repeated while the write commands stored in the command queue512 are processed.

The controller 130 may calculate an available processing time of theother commands excluding the write commands among the commands stored inthe command queue 512 by subtracting the write time required forprocessing the write commands stored in the command queue 512 from atimeout time of the write command stored in the command queue 512. Thetimeout time of the write commands stored in the command queue 512 maybe preset through the specification of the memory system 110. Thetimeout time may be decided based on a write command which is firstinputted and stored among a plurality of write commands stored in thecommand queue 512.

The controller 130 may preferentially process the other commands storedin the command queue 512 until the available processing time. After theavailable processing time, the controller 130 may preferentially processthe write commands stored in the command queue 512.

For example, suppose that the preset size contained in the secondinformation stored in the information storage 530 is 128 Kbyte.Furthermore, assuming that the number of write commands stored in thecommand queue 512 is 10 and the size of write data corresponding to onewrite command is 256 Kbyte, the entire size of write data correspondingto the write commands stored in the command queue 512 may correspond to2,560 Kbyte. Furthermore, suppose that a time required for writing writedata having the preset size of 128 Kbyte to the nonvolatile memory 150is 1 ms, the preset time contained in the third information of theinformation storage 530 is 100 ms, and the timeout time of the writecommands stored in the command queue 512 is 5,000 ms.

In this state, the controller 130 may compare the preset size of 128Kbyte to the entire size (2,560 Kbyte) of the write data correspondingto the write commands stored in the command queue 512, and determinethat the controller 130 needs to enter/exit from the automatic exclusivemode a total of 20 times in order to process the write commands storedin the command queue 512.

That is, when the controller 130 writes the entire write data (2,560Kbyte) corresponding to the write commands stored in the command queue512 to the nonvolatile memory 150 according to operations 1306, 1307 ofoperation 1302, the controller 130 needs to enter/exit from theautomatic exclusive mode at each preset size of 128 Kbyte. Therefore, inorder to write the entire write data (2,560 Kbyte) corresponding to thewrite commands stored in the command queue 512 to the nonvolatile memory150, the controller 130 needs to enter/exit from the automatic exclusivemode a total of 20 times.

The controller 130 may multiply the time required for writing the presetsize (128 Kbyte) of write data to the nonvolatile memory 150 by theprocessing number (1 ms×20 times). The controller 130 may determine thatthe time required for processing the write commands stored in thecommand queue is 20 ms.

The controller 130 may multiply the preset time of 100 ms correspondingto the entry period of the automatic exclusive mode by the calculatedprocessing number of 20 times (100 ms×20 times). The controller 130 maydetermine that the entry time of the entry period of the automaticexclusive mode which is repeated while the write commands stored in thecommand queue 512 are processed is a total of 2,000 ms.

The controller 130 may add the processing time (20 ms) of the writecommands stored in the command queue 512 and the entry time (2,000 ms)of the entry period of the automatic exclusive period which is repeatedwhile the write commands stored in the command queue 512 are processed(20 ms+2,000 ms). The controller 130 may determine that the write timerequired for processing the write commands stored in the command queue512 is 2,020 ms.

The controller 130 may subtract the write time (2,020 ms) required forprocessing the write commands stored in the command queue 512 from thetimeout time (5,000 ms) of the write command stored in the command queue512 (5,000 ms-2,020 ms). The controller 130 may determine that theavailable processing time of the other commands except the writecommands among the commands stored in the command queue 512 is 3,980 ms.

The controller 130 may preferentially process the other commandsexcluding the write commands among the commands stored in the commandqueue 512 until the available processing time of 3,980 ms. After theavailable processing time, the controller 130 may preferentially processthe write commands among the commands stored in the command queue 512for residual 2,020 ms until the write timeout of 5,000 ms.

The other commands excluding the write commands among the commandsstored in the command queue 512 may representatively indicate readcommands. Depending on design, however, the other commands may indicateother commands.

Therefore, the controller 130 can avoid or prevent a delay of a readcommand requested from the host 102 by an entry into/exit from theautomatic exclusive mode in the start period of the automatic exclusivemode as much as possible, and simultaneously prevent a write commandfrom being discarded when the write command is not processed until thetimeout.

As illustrated in FIG. 5, the controller 130 may include the processor134. The processor 134 may include a host controller 510 and a memorycontroller 520. Therefore, operations 1301 to 1308 of the controller 130may be narrowed to operations of the host controller 510 and the memorycontroller 520 which are included in the processor 134 of the controller130. However, the configuration in which operations 1301 to 1308 of thecontroller 130 are narrowed to the operations of the host controller 510and the memory controller 520 included in the processor 134 of thecontroller 130 is only an example, and operations 1301 to 1308 of thecontroller 130 can be implemented through various other components,depending on design.

The host controller 510 may include the command queue 512. The hostcontroller 510 may process an operation between the host 102 and thehost controller 510. For example, referring to FIG. 1, the hostcontroller 510 and the memory controller 520 may be included in theprocessor 134 and coupled to each other. The host controller 510 mayprocess an operation between the host 102 and the host controller 510through the host interface 132.

The memory controller 520 may be coupled to the host controller 510. Thememory controller 520 may process an operation between the nonvolatilememory 150 and the memory controller 520.

For example, referring to FIG. 1, the memory controller 520 and the hostcontroller 510 may be included in the processor 134 and coupled to eachother. The memory controller 520 may process an operation between thenonvolatile memory 150 and the memory controller 520 through the memoryinterface 142.

As illustrated in FIGS. 6 and 7, operations 1301 to 1308 of thecontroller 130 may be described in more detail by describing theoperations of the host controller 510 and the memory controller 520which are included in the processor 134 of the controller 130.

Specifically, referring to FIG. 6, the host controller 510 may check thefirst to third information stored in the information storage 530 atoperation 5101.

The host controller 510 may switch the state of the memory system 110 toa busy state in response to an entry into the automatic exclusive modein the start period of the automatic exclusive mode, which can berecognized by checking the first to third information stored in theinformation storage 530 through operation 5101. The host controller 510may inform the host 102 of the switched state, at operation 5108.

Since the host 102 recognizes through operation 5108 of the hostcontroller 510 that the memory system 110 is busy, the host controller510 may not receive an arbitrary request such as a read request or awrite request entered from the host 102 in the entry period of theautomatic exclusive mode.

The host controller 510 may switch the state of the memory system 110 toa ready state in response to an exit from the automatic exclusive modein the start period of the automatic exclusive mode, which can berecognized by checking the first to third information stored in theinformation storage 530 through operation 5101. The host controller 510may inform the host 102 of the switched state, at operation 5109.

Since the host 102 recognizes through operation 5109 of the hostcontroller 510 that the memory system 110 is ready, the host controller510 may receive an arbitrary request such as a read request or a writerequest entered from the host 102 after exiting from the automaticexclusive mode.

The host controller 510 can check the values of the first to thirdinformation stored in the information storage 530 through operation5101. However, the host controller 510 may not adjust the values of thefirst to third information stored in the information storage 530. Thatis, only the memory controller 520 may have an authority to adjust thevalues of the first to third information stored in the informationstorage 530.

When the result obtained by checking the first information of theinformation storage 530 indicates that the automatic exclusive mode wasstarted, the host controller 510 may additionally check the second andthird information to perform the preset operation described at operation1304. On the other hand, when the result indicates that the automaticexclusive mode was ended, the host controller 510 may not check thesecond and third information so that the preset operation may be notperformed.

Therefore, when the result obtained by checking the first informationstored in the information storage 530 indicates that the automaticexclusive mode was started, the host controller 510 may compare thepreset size recognized by checking the second information stored in theinformation storage 530 to the entire size of write data correspondingto the write commands among the commands stored in the command queue512. Then, the host controller 510 may calculate the number of entriesinto/exits from the automatic exclusive mode, which is required forprocessing the write commands stored in the command queue 512, as theprocessing number according to the comparison result, at operation 5102.

The host controller 510 may calculate the processing time of the writecommands stored in the command queue 512 by multiplying the processingnumber calculated through operation 5102 by the time required forwriting the preset size of write data to the nonvolatile memory 150, atoperation 5103.

The host controller 510 may calculate the entry time of the entry periodof the automatic exclusive mode which is repeated while the writecommands stored in the command queue 512 are processed, by multiplyingthe processing number calculated through operation 5102 by the presettime which can be recognized by checking the third information of theinformation storage 530, at operation 5104.

The host controller 510 may calculate a write time required forprocessing the write commands stored in the command queue 512 by addingthe processing time of the write commands stored in the command queue512 at operation 5103 and the entry time of the entry period of theautomatic exclusive period which is repeated while the write commandsstored in the command queue 512 are processed at operation 5104, atoperation 5105.

The host controller 510 may calculates an available processing time ofthe other commands excluding the write commands among the commandsstored in the command queue 512 by subtracting the write time requiredfor processing the write command stored in the command queue 512 atoperation 5105 from the timeout time of the write commands stored in thecommand queue 512, at operation 5106. The timeout time of the writecommands stored in the command queue 512 may be preset through thespecification of the memory system 110. The timeout time may be decidedbased on the write command which is first inputted and stored among theplurality of write commands stored in the command queue 512.

The host controller 510 may preferentially process the other commandsstored in the command queue 512 until the available processing timecalculated through operation 5106. After the available processing time,the host controller 510 may preferentially process the write commandsstored in the command queue 512.

For example, suppose that the preset size contained in the secondinformation of the information storage 530 is 128 Kbyte. Furthermore,when it is assumed that the number of write commands stored in thecommand queue 512 is 10 and the size of write data corresponding to onewrite command is 256 Kbyte, the entire size of write data correspondingto the write commands stored in the command queue 512 may correspond to2,560 Kbyte. Furthermore, suppose that the time required for writingwrite data having the preset size of 128 Kbyte to the nonvolatile memory150 is 1 ms, the preset time contained in the third information storedin the information storage 530 is 100 ms, and the timeout time of thewrite commands stored in the command queue 512 is 5,000 ms.

In this state, as described above at operation 5102, the host controller510 may compare the preset size of 128 Kbyte to the entire size (2,560Kbyte) of the write data corresponding to the write commands stored inthe command queue 512. The host controller 510 may determine that thehost controller 510 needs to enter/exit from the automatic exclusivemode a total of 20 times in order to process the write commands storedin the command queue 512.

That is, when the host controller 510 writes the entire write data(2,560 Kbyte) corresponding to the write commands stored in the commandqueue 512 to the nonvolatile memory 150 as described above at operations1306 and 1307 of operation 1302, the host controller 510 needs toenter/exit from the automatic exclusive mode at each preset size of 128Kbyte. Therefore, in order to process the entire write data (2,560Kbyte) corresponding to the write commands stored in the command queue512 to the nonvolatile memory 150 through the memory controller 520, thehost controller 510 needs to enter/exit from the automatic exclusivemode by a total of 20 times.

The host controller 510 may multiply the time required for writing thepreset size (128 Kbyte) of write data to the nonvolatile memory 150 bythe processing number (1 ms×20 times) as described above at operation5103. The host controller 510 may determine that the time required forprocessing the write commands stored in the command queue is 20 ms.

The host controller 510 may multiply the preset time of 100 mscorresponding to the entry period of the automatic exclusive mode by thecalculated processing number of 20 times (100 ms×20 times) as describedabove at operation 5103. The host controller 510 may determine that theentry time of the entry period of the automatic exclusive mode which isrepeated while the write commands stored in the command queue 512 areprocessed is a total of 2,000 ms.

As described above at operation 5105, the host controller 510 may addthe processing time (20 ms) of the write commands stored in the commandqueue 512 and the entry time (2,000 ms) of the entry period of theautomatic exclusive period which is repeated while the write commandsstored in the command queue 512 are processed (20 ms+2,000 ms). The hostcontroller 510 may determine that the write time required for processingthe write commands stored in the command queue 512 is 2,020 ms.

As described above at operation 5106, the host controller 510 maysubtract the write time (2,020 ms) required for processing the writecommands stored in the command queue 512 from the timeout time (5,000ms) of the write commands stored in the command queue 512 (5,000ms-2,020 ms), The host controller 510 may determine that the availableprocessing time of the other commands except the write commands amongthe commands stored in the command queue 512 is 3,980 ms.

As described above at operation 5107, the host controller 510 maypreferentially process the other commands except the write commandsamong the commands stored in the command queue 512 until the availableprocessing time of 3,980 ms. After the available processing time, thehost controller 510 may preferentially process the write commands amongthe commands stored in the command queue 512 for residual 2,020 ms untilthe write timeout of 5,000 ms.

The other commands excluding the write commands among the commandsstored in the command queue 512 may representatively indicate readcommands. Depending on a designer's selection, however, the othercommands may indicate other commands.

Therefore, the host controller 510 can avoid or prevent a delay of aread command requested from the host 102 by an entry into/exit from theautomatic exclusive mode in the start period of the automatic exclusivemode as much as possible, and simultaneously prevent a write commandfrom being discarded when the write command is not processed until thetimeout.

Referring to FIG. 7, the memory controller 520 may check the first tothird information stored in the information storage 530 at operation5203.

The memory controller 520 may write data corresponding to a writecommand stored in the command queue 512 to the nonvolatile memory 150according to a request of the host controller 510 at the exit period ofthe automatic exclusive mode in the start period of the automaticexclusive mode, which can be recognized in response to a result obtainedby checking the first to third information stored in the informationstorage 530 through operation 5203, that is, after exiting from theautomatic exclusive mode through operation 5206 which will be describedlater, at operation 5204.

The memory controller 520 may enter the automatic exclusive mode byadjusting the second information stored in the information storage 530,when the size of the write data written to the nonvolatile memory 150through operation 5204 becomes the preset size which can be recognizedthrough operation 5203 at the exit period of the automatic exclusivemode in the start period of the automatic exclusive mode, which can berecognized through the result obtained by checking the first to thirdinformation stored in the information storage 530 through operation5203, that is, after exiting from the automatic exclusive mode throughoperation 5206 which will be described later, at operation 5205.

The memory controller 520 may exit from the automatic exclusive mode byadjusting the second information stored in the information storage 530at a point of time that the preset time recognized through operation5203 has elapsed from the entry period of the automatic exclusive modein the start period of the automatic exclusive mode, which can berecognized through the result obtained by checking the first to thirdinformation stored in the information storage 530 through operation5203, that is, the point of time that the memory controller 520 enteredthe automatic exclusive mode through operation 5205, at operation 5206.

The memory controller 520 may check the state of the nonvolatile memory150 at operation 5201. At this time, the operation of checking the stateof the nonvolatile memory 150 may include an operation of checking theratio of free memory blocks among the memory blocks BLOCK<1:6> includedin the nonvolatile memory 150.

In the embodiment, the operation of checking the ratio of free memoryblocks among the memory blocks BLOCK<1:6> included in the nonvolatilememory 150 at operation 5201 may be exemplified as the operation ofchecking the state of the nonvolatile memory 150. However, this is onlyan example, and the state of the nonvolatile memory 150 can be checkedthrough another method.

The memory controller 520 may adjust the first to third information ofthe information storage 530 according to the check result of operation5201, to adjust information on whether to start/exit the automaticexclusive mode and the entry and exit points of the automatic exclusivemode, at operation 5202.

Specifically, the memory controller 520 may check the ratio of freememory blocks among the memory blocks BLOCK<1:6> included in thenonvolatile memory 150 through operation 5201. The memory controller 520may adjust the first information stored in the information storage 530through operation 5202 according to the check result, thereby selectingwhether to start/exit the automatic exclusive mode.

When the check result indicates that the ratio of free memory blocks isequal to or less than the preset ratio, the memory controller 520continue to be in the automatic exclusive mode if the automaticexclusive mode was already started, or start the automatic exclusivemode if the automatic exclusive mode was ended.

On the other hand, when the check result indicates that the ratio offree memory blocks exceeds the preset ratio, the memory controller 520can retain end state the automatic exclusive mode when the automaticexclusive mode was already started, or retain the end state of theautomatic exclusive mode when the automatic exclusive mode was ended.

When entering the automatic exclusive mode to perform a merge operationafter starting the automatic exclusive mode according to the checkresult of operation 5201, the memory controller 520 may check the totalnumber of valid pages included in victim memory blocks among the memoryblocks BLOCK<1:6> included in the nonvolatile memory 150 throughoperation 5201, based on the preset number. The memory controller 520may adjust the value of the second or third information stored in theinformation storage 530 through operation 5202, according to the checkresult.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is equal to or more than a presetnumber, the memory controller 520 may decrease the preset size containedin the second information stored in the information storage 530, suchthat the entry into the automatic exclusive mode through operation 5205is more frequently repeated.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is less than the preset number,the memory controller 520 may increase the preset size contained in thesecond information stored in the information storage 530, such that theentry into the automatic exclusive mode through operation 5205 is lessfrequently repeated.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is equal to or more than thepreset number, the memory controller 520 may increase the preset lengthcontained in the third information stored in the information storage530, such that the time interval from the entry point of the automaticexclusive mode through operation 5205 to the exit point of the automaticexclusive mode through operation 5206 is increased.

During the merge operation, when the total number of valid pagesincluded in the victim memory blocks among the memory blocks BLOCK<1:6>included in the nonvolatile memory 150 is less than the preset number,the memory controller 520 may decrease the preset length contained inthe third information stored in the information storage 530, such thatthe time interval from the entry point of the automatic exclusive modethrough operation 5205 to the exit point of the automatic exclusive modethrough operation 5206 is decreased.

For reference, the memory controller 520 may adjust only the second orthird information or both of the second and third information stored inthe information storage 530 through one adjusting operation. Theadjusting operation of the memory controller 520 to adjust the second orthird information stored in the information storage 530 may be changeddepending on design.

The memory controller 520 may flush data stored in the volatile memory144 to the nonvolatile memory 150 in response to the entry into theautomatic exclusive mode in the start period of the automatic exclusivemode through operations 5202 and 5205.

In this case, the memory controller 520 may exclusively use the entireregion of the volatile memory 144 to perform a merge operation duringthe entry period of the automatic exclusive mode.

At this time, the operation of flushing the data stored in the volatilememory 144 to the nonvolatile memory 150 may indicate that all of thedata stored in the volatile memory 144 are copied and stored into apreset region of the nonvolatile memory 150. After the flush operation,all data in the volatile memory 144 are no longer necessary to beretained so that the memory controller 520 may discard all of the datastored in the volatile memory 144. Then, the memory controller 520 mayexclusively use the entire region of the volatile memory 144, which isallocated for storing data, to perform a merge operation.

Furthermore, the memory controller 520 may discard data updated into thenonvolatile memory 150 among the data stored in the volatile memory 144,in response to the entry into the automatic exclusive mode in the startperiod of the automatic exclusive mode through operations 5202 and 5205.

In this case, the memory controller 520 may exclusively use a widerregion than a region designated for a general merge operation in thevolatile memory 144, to perform the merge operation during the entryperiod of the automatic exclusive mode.

As described above with reference to FIG. 1, the volatile memory 144 canbe used for various uses, for example, a write buffer/cache, a readbuffer/cache and a map buffer/cache. Therefore, the internal storagespace of the volatile memory 144 may be divided into various regionsdepending on the uses. Thus, a part of the internal storage region ofthe volatile memory 144 may be previously designated for a mergeoperation.

At this time, the memory controller 520 in accordance with theembodiment may discard data updated into the nonvolatile memory 150among data stored in a region which is not designated for a mergeoperation in the storage space of the volatile memory 144, in responseto the entry into the automatic exclusive mode in the start period ofthe automatic exclusive mode through operations 5202 and 5205.Therefore, the memory controller 520 in accordance with the embodimentcan exclusively use a wider region than a region designated for ageneral merge operation in the volatile memory 144, to perform the mergeoperation during the entry period of the automatic exclusive mode.

The data updated into the nonvolatile memory 150 among the data storedin the volatile memory 144 may indicate data which have been alreadystored into the nonvolatile memory 150 through an operation such as acheckpoint, among the data stored in the nonvolatile memory 144. Forthis reason, the memory controller 520 can discard the data updated intothe nonvolatile memory 150 among the data stored in the volatile memory144 in the entry period of the automatic exclusive mode, and then usethe corresponding region (i.e., previously storing discarded data andnow ready to be allocated) for a merge operation.

FIGS. 8 to 16 are diagrams schematically illustrating applicationexamples of the data processing system of FIG. 1.

FIG. 8 is a diagram schematically illustrating an example of the dataprocessing system including the memory system in accordance with thepresent embodiment. FIG. 8 schematically illustrates a memory cardsystem to which the memory system in accordance with the presentembodiment is applied.

Referring to FIG. 8, the memory card system 6100 may include a memorycontroller 6120, a memory device 6130 and a connector 6110.

The memory controller 6120 may be connected to the memory device 6130embodied by a nonvolatile memory. The memory controller 6120 may beconfigured to access the memory device 6130. By way of example and notlimitation, the memory controller 6120 may be configured to controlread, write, erase and background operations of the memory device 6130.The memory controller 6120 may be configured to provide an interfacebetween the memory device 6130 and a host, and use a firmware forcontrolling the memory device 6130. That is, the memory controller 6120may correspond to the controller 130 of the memory system 110 describedwith reference to FIGS. 1 and 5, and the memory device 6130 maycorrespond to the memory device 150 of the memory system 110 describedwith reference to FIGS. 1 and 5.

Thus, the memory controller 6120 may include a RAM, a processing unit, ahost interface, a memory interface and an error correction component.The memory controller 130 may further include the elements shown in FIG.5.

The memory controller 6120 may communicate with an external device, forexample, the host 102 of FIG. 1 through the connector 6110. For example,as described with reference to FIG. 1, the memory controller 6120 may beconfigured to communicate with an external device under one or more ofvarious communication protocols such as universal serial bus (USB),multimedia card (MMC), embedded MMC (eMMC), peripheral componentinterconnection (PCI), PCI express (PCIe), Advanced TechnologyAttachment (ATA), Serial-ATA, Parallel-ATA, small computer systeminterface (SCSI), enhanced small disk interface (EDSI), Integrated DriveElectronics (IDE), Firewire, universal flash storage (UFS), WIFI andBluetooth. Thus, the memory system and the data processing system inaccordance with the present embodiment may be applied to wired/wirelesselectronic devices or particularly mobile electronic devices.

The memory device 6130 may be implemented by a nonvolatile memory. Forexample, the memory device 6130 may be implemented by variousnonvolatile memory devices such as an erasable and programmable ROM(EPROM), an electrically erasable and programmable ROM (EEPROM), a NANDflash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistiveRAM (ReRAM), a ferroelectric RAM (FRAM) and a spin torque transfermagnetic RAM (STT-RAM). The memory device 6130 may include a pluralityof dies as in the memory device 150 of FIG. 5.

The memory controller 6120 and the memory device 6130 may be integratedinto a single semiconductor device. For example, the memory controller6120 and the memory device 6130 may construct a solid state driver (SSD)by being integrated into a single semiconductor device. Also, the memorycontroller 6120 and the memory device 6130 may construct a memory cardsuch as a PC card (PCMCIA: Personal Computer Memory Card InternationalAssociation), a compact flash (CF) card, a smart media card (e.g., a SMand a SMC), a memory stick, a multimedia card (e.g., a MMC, a RS-MMC, aMMCmicro and an eMMC), an SD card (e.g., a SD, a miniSD, a microSD and aSDHC) and a universal flash storage (UFS).

FIG. 9 is a diagram schematically illustrating an example of the dataprocessing system including the memory system in accordance with theembodiment.

Referring to FIG. 9, the data processing system 6200 may include amemory device 6230 having one or more nonvolatile memories and a memorycontroller 6220 for controlling the memory device 6230. The dataprocessing system 6200 illustrated in FIG. 9 may serve as a storagemedium such as a memory card (CF, SD, micro-SD or the like) or USBdevice, as described with reference to FIG. 1. The memory device 6230may correspond to the memory device 150 in the memory system 110illustrated in FIGS. 1 and 5. The memory controller 6220 may correspondto the controller 130 in the memory system 110 illustrated in FIGS. 1and 5.

The memory controller 6220 may control a read, write or erase operationon the memory device 6230 in response to a request of the host 6210. Thememory controller 6220 may include one or more CPUs 6221, a buffermemory such as RAM 6222, an ECC circuit 6223, a host interface 6224 anda memory interface such as an NVM interface 6225.

The CPU 6221 may control overall operations on the memory device 6230,for example, read, write, file system management and bad page managementoperations. The RAM 6222 may be operated according to control of the CPU6221. The RAM 6222 may be used as a work memory, buffer memory or cachememory. When the RAM 6222 is used as a work memory, data processed bythe CPU 6221 may be temporarily stored in the RAM 6222. When the RAM6222 is used as a buffer memory, the RAM 6222 may be used for bufferingdata transmitted to the memory device 6230 from the host 6210 ortransmitted to the host 6210 from the memory device 6230. When the RAM6222 is used as a cache memory, the RAM 6222 may assist the low-speedmemory device 6230 to operate at high speed.

The ECC circuit 6223 may correspond to the ECC component 138 of thecontroller 130 illustrated in FIG. 1. As described with reference toFIG. 1, the ECC circuit 6223 may generate an ECC (Error Correction Code)for correcting a fail bit or error bit of data provided from the memorydevice 6230. The ECC circuit 6223 may perform error correction encodingon data provided to the memory device 6230, thereby forming data with aparity bit. The parity bit may be stored in the memory device 6230. TheECC circuit 6223 may perform error correction decoding on data outputtedfrom the memory device 6230. At this time, the ECC circuit 6223 maycorrect an error using the parity bit. For example, as described withreference to FIG. 1, the ECC circuit 6223 may correct an error using theLDPC code, BCH code, turbo code, Reed-Solomon code, convolution code,RSC or coded modulation such as TCM or BCM.

The memory controller 6220 may transmit/receive data to/from the host6210 through the host interface 6224. The memory controller 6220 maytransmit/receive data to/from the memory device 6230 through the NVMinterface 6225. The host interface 6224 may be connected to the host6210 through a PATA bus, SATA bus, SCSI, USB, PCIe or NAND interface.The memory controller 6220 may have a wireless communication functionwith a mobile communication protocol such as WiFi or Long Term Evolution(LTE). The memory controller 6220 may be connected to an externaldevice, for example, the host 6210 or another external device, and thentransmit/receive data to/from the external device. Particularly, as thememory controller 6220 is configured to communicate with the externaldevice through one or more of various communication protocols, thememory system and the data processing system in accordance with thepresent embodiment may be applied to wired/wireless electronic devicesor particularly a mobile electronic device.

FIG. 10 is a diagram schematically illustrating an example of the dataprocessing system including the memory system in accordance with theembodiment. FIG. 10 schematically illustrates an SSD to which the memorysystem in accordance with the embodiment is applied.

Referring to FIG. 10, the SSD 6300 may include a controller 6320 and amemory device 6340 including a plurality of nonvolatile memories. Thecontroller 6320 may correspond to the controller 130 in the memorysystem 110 of FIGS. 1 and 5. The memory device 6340 may correspond tothe memory device 150 in the memory system of FIGS. 1 and 5.

More specifically, the controller 6320 may be connected to the memorydevice 6340 through a plurality of channels CH1 to CHi. The controller6320 may include one or more processors 6321, a buffer memory 6325, anECC circuit 6322, a host interface 6324 and a memory interface, forexample, a nonvolatile memory interface 6326.

The buffer memory 6325 may temporarily store data provided from the host6310 or data provided from a plurality of flash memories NVM included inthe memory device 6340, or temporarily store meta data of the pluralityof flash memories NVM, for example, map data including a mapping table.The buffer memory 6325 may be embodied by volatile memories such asDRAM, SDRAM, DDR SDRAM, LPDDR SDRAM and GRAM or nonvolatile memoriessuch as FRAM, ReRAM, STT-MRAM and PRAM. For convenience of description,FIG. 9 illustrates that the buffer memory 6325 exists in the controller6320. However, the buffer memory 6325 may exist outside the controller6320.

The ECC circuit 6322 may calculate an ECC value of data to be programmedto the memory device 6340 during a program operation. The ECC circuit6322 may perform an error correction operation on data read from thememory device 6340 based on the ECC value during a read operation. TheECC circuit 6322 may perform an error correction operation on datarecovered from the memory device 6340 during a failed data recoveryoperation.

The host interface 6324 may provide an interface function with anexternal device, for example, the host 6310. The nonvolatile memoryinterface 6326 may provide an interface function with the memory device6340 connected through the plurality of channels.

Furthermore, a plurality of SSDs 6300 to which the memory system 110 ofFIGS. 1 and 5 is applied may be provided to embody a data processingsystem, for example, RAID (Redundant Array of Independent Disks) system.At this time, the RAID system may include the plurality of SSDs 6300 anda RAID controller for controlling the plurality of SSDs 6300. When theRAID controller performs a program operation in response to a writecommand provided from the host 6310, the RAID controller may select oneor more memory systems or SSDs 6300 according to a plurality of RAIDlevels, that is, RAID level information of the write command providedfrom the host 6310 in the SSDs 6300. The RAID controller may output datacorresponding to the write command to the selected SSDs 6300.Furthermore, when the RAID controller performs a read command inresponse to a read command provided from the host 6310, the RAIDcontroller may select one or more memory systems or SSDs 6300 accordingto a plurality of RAID levels, that is, RAID level information of theread command provided from the host 6310 in the SSDs 6300. The RAIDcontroller may provide data read from the selected SSDs 6300 to the host6310.

FIG. 11 is a diagram schematically illustrating an example of the dataprocessing system including the memory system in accordance with theembodiment. FIG. 11 schematically illustrates an embedded Multi-MediaCard (eMMC) to which the memory system in accordance with the embodimentis applied.

Referring to FIG. 11, the eMMC 6400 may include a controller 6430 and amemory device 6440 embodied by one or more NAND flash memories. Thecontroller 6430 may correspond to the controller 130 in the memorysystem 110 of FIGS. 1 and 5. The memory device 6440 may correspond tothe memory device 150 in the memory system 110 of FIGS. 1 and 5.

More specifically, the controller 6430 may be connected to the memorydevice 6440 through a plurality of channels. The controller 6430 mayinclude one or more cores 6432, a host interface 6431 and a memoryinterface, for example, a NAND interface 6433.

The core 6432 may control overall operations of the eMMC 6400. The hostinterface 6431 may provide an interface function between the controller6430 and the host 6410. The NAND interface 6433 may provide an interfacefunction between the memory device 6440 and the controller 6430. Forexample, the host interface 6431 may serve as a parallel interface, forexample, MMC interface as described with reference to FIG. 1.Furthermore, the host interface 6431 may serve as a serial interface,for example, UHS ((Ultra High Speed)-I/UHS-II) interface.

FIGS. 12 to 15 are diagrams schematically illustrating other examples ofthe data processing system including the memory system in accordancewith the embodiment. FIGS. 12 to 15 schematically illustrate UFS(Universal Flash Storage) systems to which the memory system inaccordance with the embodiment is applied.

Referring to FIGS. 12 to 15, the UFS systems 6500, 6600, 6700, 6800 mayinclude hosts 6510, 6610, 6710, 6810, UFS devices 6520, 6620, 6720, 6820and UFS cards 6530, 6630, 6730, 6830, respectively. The hosts 6510,6610, 6710, 6810 may serve as application processors of wired/wirelesselectronic devices or particularly mobile electronic devices, the UFSdevices 6520, 6620, 6720, 6820 may serve as embedded UFS devices, andthe UFS cards 6530, 6630, 6730, 6830 may serve as external embedded UFSdevices or removable UFS cards.

The hosts 6510, 6610, 6710, 6810, the UFS devices 6520, 6620, 6720, 6820and the UFS cards 6530, 6630, 6730, 6830 in the respective UFS systems6500, 6600, 6700, 6800 may communicate with external devices, forexample, wired/wireless electronic devices or particularly mobileelectronic devices through UFS protocols, and the UFS devices 6520,6620, 6720, 6820 and the UFS cards 6530, 6630, 6730, 6830 may beembodied by the memory system 110 illustrated in FIGS. 1 and 5. Forexample, in the UFS systems 6500, 6600, 6700, 6800, the UFS devices6520, 6620, 6720, 6820 may be embodied in the form of the dataprocessing system 6200, the SSD 6300 or the eMMC 6400 described withreference to FIGS. 9 to 11, and the UFS cards 6530, 6630, 6730, 6830 maybe embodied in the form of the memory card system 6100 described withreference to FIG. 8.

Furthermore, in the UFS systems 6500, 6600, 6700, 6800, the hosts 6510,6610, 6710, 6810, the UFS devices 6520, 6620, 6720, 6820 and the UFScards 6530, 6630, 6730, 6830 may communicate with each other through anUFS interface, for example, MIPI M-PHY and MIPI UniPro (UnifiedProtocol) in MIPI (Mobile Industry Processor Interface). Furthermore,the UFS devices 6520, 6620, 6720, 6820 and the UFS cards 6530, 6630,6730, 6830 may communicate with each other through various protocolsother than the UFS protocol, for example, an UFDs, a MMC, a SD, amini-SD, and a micro-SD.

In the UFS system 6500 illustrated in FIG. 12, each of the host 6510,the UFS device 6520 and the UFS card 6530 may include UniPro. The host6510 may perform a switching operation in order to communicate with theUFS device 6520 and the UFS card 6530. In particular, the host 6510 maycommunicate with the UFS device 6520 or the UFS card 6530 through linklayer switching, for example, L3 switching at the UniPro. At this time,the UFS device 6520 and the UFS card 6530 may communicate with eachother through link layer switching at the UniPro of the host 6510. Inthe present embodiment, the configuration in which one UFS device 6520and one UFS card 6530 are connected to the host 6510 has beenexemplified for convenience of description. However, a plurality of UFSdevices and UFS cards may be connected in parallel or in the form of astar to the host 6410. The form of a star is a sort of arrangementswhere a single centralized component is coupled to plural devices forparallel processing. A plurality of UFS cards may be connected inparallel or in the form of a star to the UFS device 6520 or connected inseries or in the form of a chain to the UFS device 6520.

In the UFS system 6600 illustrated in FIG. 13, each of the host 6610,the UFS device 6620 and the UFS card 6630 may include UniPro, and thehost 6610 may communicate with the UFS device 6620 or the UFS card 6630through a switching module 6640 performing a switching operation, forexample, through the switching module 6640 which performs link layerswitching at the UniPro, for example, L3 switching. The UFS device 6620and the UFS card 6630 may communicate with each other through link layerswitching of the switching module 6640 at UniPro. In the presentembodiment, the configuration in which one UFS device 6620 and one UFScard 6630 are connected to the switching module 6640 has beenexemplified for convenience of description. However, a plurality of UFSdevices and UFS cards may be connected in parallel or in the form of astar to the switching module 6640, and a plurality of UFS cards may beconnected in series or in the form of a chain to the UFS device 6620.

In the UFS system 6700 illustrated in FIG. 14, each of the host 6710,the UFS device 6720 and the UFS card 6730 may include UniPro, and thehost 6710 may communicate with the UFS device 6720 or the UFS card 6730through a switching module 6740 performing a switching operation, forexample, through the switching module 6740 which performs link layerswitching at the UniPro, for example, L3 switching. At this time, theUFS device 6720 and the UFS card 6730 may communicate with each otherthrough link layer switching of the switching module 6740 at the UniPro,and the switching module 6740 may be integrated as one module with theUFS device 6720 inside or outside the UFS device 6720. In the presentembodiment, the configuration in which one UFS device 6720 and one UFScard 6730 are connected to the switching module 6740 has beenexemplified for convenience of description. However, a plurality ofmodules each including the switching module 6740 and the UFS device 6720may be connected in parallel or in the form of a star to the host 6710or connected in series or in the form of a chain to each other.Furthermore, a plurality of UFS cards may be connected in parallel or inthe form of a star to the UFS device 6720.

In the UFS system 6800 illustrated in FIG. 15, each of the host 6810,the UFS device 6820 and the UFS card 6830 may include M-PHY and UniPro.The UFS device 6820 may perform a switching operation in order tocommunicate with the host 6810 and the UFS card 6830. In particular, theUFS device 6820 may communicate with the host 6810 or the UFS card 6830through a switching operation between the M-PHY and UniPro module forcommunication with the host 6810 and the M-PHY and UniPro module forcommunication with the UFS card 6830, for example, through a target ID(Identifier) switching operation. At this time, the host 6810 and theUFS card 6830 may communicate with each other through target IDswitching between the M-PHY and UniPro modules of the UFS device 6820.In the present embodiment, the configuration in which one UFS device6820 is connected to the host 6810 and one UFS card 6830 is connected tothe UFS device 6820 has been exemplified for convenience of description.However, a plurality of UFS devices may be connected in parallel or inthe form of a star to the host 6810, or connected in series or in theform of a chain to the host 6810, and a plurality of UFS cards may beconnected in parallel or in the form of a star to the UFS device 6820,or connected in series or in the form of a chain to the UFS device 6820.

FIG. 16 is a diagram schematically illustrating an example of the dataprocessing system including the memory system in accordance with anembodiment. FIG. 16 is a diagram schematically illustrating a usersystem to which the memory system in accordance with the embodiment isapplied.

Referring to FIG. 16, the user system 6900 may include an applicationprocessor 6930, a memory module 6920, a network module 6940, a storagemodule 6950 and a user interface 6910.

More specifically, the application processor 6930 may drive componentsincluded in the user system 6900, for example, an OS, and includecontrollers, interfaces and a graphic engine which control thecomponents included in the user system 6900. The application processor6930 may be provided as System-on-Chip (SoC).

The memory module 6920 may be used as a main memory, work memory, buffermemory or cache memory of the user system 6900. The memory module 6920may include a volatile RAM such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM,DDR3 SDRAM, LPDDR SDARM, LPDDR3 SDRAM or LPDDR3 SDRAM or a nonvolatileRAM such as PRAM, ReRAM, MRAM or FRAM. For example, the applicationprocessor 6930 and the memory module 6920 may be packaged and mounted,based on POP (Package on Package).

The network module 6940 may communicate with external devices. Forexample, the network module 6940 may not only support wiredcommunication, but also support various wireless communication protocolssuch as code division multiple access (CDMA), global system for mobilecommunication (GSM), wideband CDMA (WCDMA), CDMA-2000, time divisionmultiple access (TDMA), long term evolution (LTE), worldwideinteroperability for microwave access (Wimax), wireless local areanetwork (WLAN), ultra-wideband (UWB), Bluetooth, wireless display(WI-DI), thereby communicating with wired/wireless electronic devices orparticularly mobile electronic devices. Therefore, the memory system andthe data processing system, in accordance with an embodiment of thepresent invention, can be applied to wired/wireless electronic devices.The network module 6940 may be included in the application processor6930.

The storage module 6950 may store data, for example, data received fromthe application processor 6930, and then may transmit the stored data tothe application processor 6930. The storage module 6950 may be embodiedby a nonvolatile semiconductor memory device such as a phase-change RAM(PRAM), a magnetic RAM (MRAM), a resistive RAM (ReRAM), a NAND flash, aNOR flash and a 3D NAND flash, and provided as a removable storagemedium such as a memory card or external drive of the user system 6900.The storage module 6950 may correspond to the memory system 110described with reference to FIGS. 1 and 5. Furthermore, the storagemodule 6950 may be embodied as an SSD, an eMMC and an UFS as describedabove with reference to FIGS. 10 to 15.

The user interface 6910 may include interfaces for inputting data orcommands to the application processor 6930 or outputting data to anexternal device. For example, the user interface 6910 may include userinput interfaces such as a keyboard, a keypad, a button, a touch panel,a touch screen, a touch pad, a touch ball, a camera, a microphone, agyroscope sensor, a vibration sensor and a piezoelectric element, anduser output interfaces such as a liquid crystal display (LCD), anorganic light emitting diode (OLED) display device, an active matrixOLED (AMOLED) display device, an LED, a speaker and a motor.

Furthermore, when the memory system 110 of FIGS. 1 and 5 is applied to amobile electronic device of the user system 6900, the applicationprocessor 6930 may control overall operations of the mobile electronicdevice. The network module 6940 may serve as a communication module forcontrolling wired/wireless communication with an external device. Theuser interface 6910 may display data processed by the processor 6930 ona display/touch module of the mobile electronic device. Further, theuser interface 6910 may support a function of receiving data from thetouch panel.

In accordance with the present embodiment, the memory system can allowan exclusive use of the nonvolatile memory in order to perform a mergeoperation in the entry period of the automatic exclusive mode, therebymaximizing the performance of the merge operation.

At this time, the memory system may select whether to start/exit theautomatic exclusive mode in response to a request of the host or aresult obtained by checking the state of the nonvolatile memory. Thememory system may automatically repeat the exit into/exit from theautomatic exclusive mode every predetermined cycle in the start periodof the automatic exclusive mode. Through these operations, the memorysystem can accurately adjust the entry/exit points of the automaticexclusive mode.

Furthermore, the memory system can calculate the performance time of theentry/exit operation of the automatic exclusive mode, which is repeatedin the start period of the automatic exclusive mode. The memory systemcan schedule a processing order of normal commands (for example, readand write commands) requested from the host. Through this operation, thememory system can avoid a timeout of the normal commands requested fromthe host by the entry into/exit from the automatic exclusive mode, whichis repeated in the start period of the automatic exclusive mode.

Although various embodiments have been described for illustrativepurposes, it will be apparent to those skilled in the art that variouschanges and modifications may be made without departing from the spiritand scope of the invention as defined in the following claims.

What is claimed is:
 1. A memory system comprising: a nonvolatile memory;a volatile memory; an information storage configured to store aninformation related to a mode; a memory controller configured to enterthe mode for performing a merge operation in the nonvolatile memory,when size of a write data transferred from a host is a predeterminedsize that depends on the information stored in the information storage;and a host controller coupled to the memory controller, and configuredto calculate a processing time of write commands related to the writedata among commands stored in a command queue and schedule a processingorder of the commands stored in the command queue according to a resultof calculation that depends on the information stored in the informationstorage, wherein the memory controller exclusively uses the volatilememory for performing the merge operation in the nonvolatile memory whenentering the mode.
 2. The memory system of claim 1, wherein theinformation storage configured to store first information indicating thestart/end states of the mode, second information indicating theentry/exit points of the mode and the predetermined size, and thirdinformation indicating a preset time.
 3. The memory system of claim 2,wherein the host controller checks the first to third information of theinformation storage in the start period of the mode recognized throughthe check result, and compares the predetermined size stored in theinformation storage to size of the write data corresponding to the writecommands stored in the command queue.
 4. The memory system of claim 3,wherein the host controller calculates the number of entries of modefrom the write commands stored in the command queue as a processingnumber, and calculates a processing time using the processing number anda time required for writing the predetermined size of write data to thenonvolatile memory.
 5. The memory system of claim 4, wherein the hostcontroller calculates an entry time of the mode by multiplying theprocessing number by the preset time recognized through the checkresult, calculates a write time by adding the processing time and entrytime, and calculates a processing of other commands by subtracting thewrite time from a timeout time.
 6. The memory system of claim 5, whereinthe host controller schedules the processing order of the commandsstored in the command queue processing the other commands until thetimeout time with preventing the write commands from being discarded. 7.The memory system of claim 1, wherein the host controller informs thehost of a signal indicating a busy state in response to the state of themode from the information storage.
 8. The memory system of claim 1,wherein the memory controller adjusts the information on whether tostart/end the mode and the entry/exit points of the mode by adjustingthe first to third information stored in the information storage inresponse to the result obtained by checking the state of the nonvolatilememory.
 9. The memory system of claim 8, wherein the memory controllerchecks the first to third information of the information storage, writesthe write data to the nonvolatile memory according to a request of thehost controller in the start period of the mode recognized through thecheck result, enters the mode by adjusting the second information of theinformation storage when the write data corresponding to thepredetermined size recognized through the check result are written tothe nonvolatile memory, and exits from the mode by adjusting the secondinformation of the information storage at a time point when the presettime recognized through the check result has elapsed from the entrypoint of the mode.
 10. An operation method of a memory system whichcomprises a memory controller, a host controller, a nonvolatile memory,a volatile memory, and an information storage for storing an informationrelated to a mode, the operation method comprising: repeatedly enteringthe mode for performing a merge operation in the nonvolatile memory,when size of a write data transferred from a host is a predeterminedsize that depends on the information of the information storage,calculating a processing time of write commands related to the writedata among commands stored in a command queue and then scheduling aprocessing order of the commands stored in the commands queue accordingto the calculation result that depends on the information stored in theinformation storage, and exclusively using the volatile memory toperform the merge operation in the nonvolatile memory when entering themode.
 11. The operation method of claim 10, wherein the informationstorage configured to store first information indicating the start/endstates of the mode, second information indicating the entry/exit pointsof the mode and the predetermined size, and third information indicatinga preset time.
 12. The operation method of claim 11, wherein thecalculating the processing time comprises: checking the first to thirdinformation of the information storage in the start period of the moderecognized thorough the check result, and comparing the predeterminedsize in the information storage to size of the write data correspondingto the write commands stored in the command queue.
 13. The operationmethod of claim 12, wherein the calculating the processing time furthercomprises: a first calculation step in which the host controllercalculates the number of entries from the write commands stored in thecommand queue as a processing number; and a second calculation step inwhich the host controller calculates a processing time using theprocessing number and a time required for writing the predetermined sizeof write data to the nonvolatile memory.
 14. The operation method ofclaim 13, wherein the calculating the processing time further comprisesa third calculation step in which the host controller calculates anentry time of the mode by multiplying the processing number by thepreset time recognized through the check result.
 15. The operatingmethod of claim 14, wherein the calculating the processing time furthercomprises: a fourth calculation step in which the host controllercalculates a write time by adding the processing time and entry time; afifth calculation step in which the host controller calculates aprocessing of other commands by subtracting the write time from atimeout time; and a processing step in which the host controllerschedules the processing order of the commands stored in the commandqueue processing the other commands until the timeout time withpreventing the write commands from being discarded.
 16. The operationmethod of claim 12, wherein the repeatedly entering the mode comprises:a second check step in which the host controller checks the first tothird information stored in the information storage; a first informingstep in which the host controller informs the host of a signalindicating a busy state in response to the state of the mode from theinformation storage, recognized through the second check state; and asecond informing step in which the host controller informs the host of asignal indicating a ready state in response to the state of the mode,recognized through the second check state.
 17. The operation method ofclaim 12, wherein the repeatedly entering the mode comprises: a thirdcheck step in which the memory controller checks the state of thenonvolatile memory; and an adjusting step in which the memory controlleradjusts the information on whether to start/end the mode and theentry/exit points of the mode by adjusting the first to thirdinformation stored in the information storage in response to the resultof the third check step.
 18. The operation method of claim 17, whereinthe repeatedly entering the mode further comprises a fourth check stepin which the memory controller checks the first to third information ofthe information storage, the entry step comprises: writing, by thememory controller, the write data to the nonvolatile memory according toa write request transferred to the memory controller from the hostcontroller in the start period of the mode, recognized through theresult of the fourth check step; and entering, by the memory controller,the mode by adjusting the second information of the information storagewhen the memory controller writes the write data corresponding to thepredetermined size recognized through the result of the fourth checkstep to the nonvolatile memory, and in the exit step, the memorycontroller exits from the mode by adjusting the second information ofthe information storage at a time point when the preset time recognizedthrough the result of the fourth check step has elapsed from the entrypoint of the mode.
 19. The memory system of claim 1, wherein the memorycontroller exclusively uses all or part region of the volatile memoryfor performing the merge operation in the nonvolatile memory whenentering the mode.
 20. The memory system of claim 19, wherein the partregion of the volatile memory comprises a region which is stored a dataupdated into the nonvolatile memory and a region which is designated forthe merge operation, among all region of the volatile memory.
 21. Theoperation method of claim 10, wherein the exclusively using the volatilememory comprises: exclusively using all region of the volatile memory toperform the merge operation in the nonvolatile memory when entering themode, or exclusively using part region of the volatile memory to performthe merge operation in the nonvolatile memory when entering the mode.22. The operation method of claim 21, wherein the part region of thevolatile memory comprises a region which is stored a data updated intothe nonvolatile memory and a region which is designated for the mergeoperation, among all region of the volatile memory.